| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
5 pcs
|
5 pcs | On Request | 1 | On Request | On Request | 2026-02-25 06:16:38 | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Halogen Free | |
| Industrial Grade | |
| SVHC Present |
The MC100EP32DG from ON Semiconductor is an integrated divide-by-2 circuit designed for ECL logic families. It features differential clock inputs and an asynchronous reset pin for synchronization.
Key electrical characteristics include a typical propagation delay of 350 ps and a maximum operating frequency greater than 4 GHz. The device supports PECL mode with a VCC range of 3.0 V to 5.5 V (VEE = 0 V) and NECL mode with a VEE range of -3.0 V to -5.5 V (VCC = 0 V).
This component includes safety clamps on inputs and an open input default state. The Q output defaults LOW with inputs open or at VEE. The MC100EP32DG is available in a SOIC-8 package, suitable for surface mount (SMD/SMT) applications.
The 100 Series includes temperature compensation. The VBB pin provides an internally generated voltage supply, which can be used as a switching reference voltage for single-ended inputs or to re-bias AC coupled inputs. Decoupling VBB and VCC with a 0.01/C0258/C0109F capacitor is recommended when VBB is used, limiting current sourcing or sinking to 0.5 mA. When not in use, VBB should be left open.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The typical propagation delay is 350 ps.
The maximum frequency is greater than 4 GHz.
It operates in PECL mode with VCC from 3.0 V to 5.5 V (VEE = 0 V) and in NECL mode with VEE from -3.0 V to -5.5 V (VCC = 0 V).
The MC100EP32DG is available in a SOIC-8 package.
Yes, it is RoHS3 Compliant.