| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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70 pcs
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70 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Lattice LFE2-50E-5FN672C is a Field Programmable Gate Array (FPGA) from the LatticeECP2/M family. It offers a logic density of 48,000 LUTs and supports up to 500 I/O pins. The device features 396,288 total RAM bits, organized into embedded block RAM and distributed RAM.
This FPGA includes embedded SERDES capabilities with data rates up to 3.125 Gbps and up to 16 channels. It also incorporates sysDSP blocks for high-performance multiply and accumulate operations, and sysCLOCK Analog PLLs and DLLs for clock management. The programmable sysI/O buffer supports a wide range of interfaces including LVTTL, LVCMOS, SSTL, HSTL, and differential standards like LVDS and LVPECL.
The LFE2-50E-5FN672C operates within a voltage range of 1.14V to 1.26V and has an operating temperature range of 0°C to 85°C (TJ). It is configured in a 672-FPBGA (27x27mm) surface mount package. Device configuration options include 1149.1 Boundary Scan compliance and an SPI boot flash interface.
The LFE2-50E-5FN672C FPGA has 48,000 logic elements.
The LFE2-50E-5FN672C has 500 I/O pins.
The operating voltage range for the LFE2-50E-5FN672C is 1.14V to 1.26V.
The LFE2-50E-5FN672C is supplied in a 672-FPBGA (27x27mm) package.
The operating temperature range for the LFE2-50E-5FN672C is 0°C to 85°C (TJ).
The LFE2-50E-5FN672C supports embedded SERDES with data rates from 250 Mbps to 3.125 Gbps and up to 16 channels.
The LFE2-50E-5FN672C features both embedded block RAM (EBR) ranging from 55 Kbits to 5308 Kbits and distributed RAM from 12 Kbits to 202 Kbits.