EPM7064AETC100-10N
Altera
The Altera EPM7064AETC100-10N is a high-performance 3.3V EEPROM-based programmable logic device. It offers fast 4.5ns pin-to-pin logic delays and supports a wide range of I/O voltage levels.
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57 pcs
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57 pcs | On Request | 1 | On Request | On Request | 1231 | On Request | On Request |
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The Altera EPM7128AETC100-5N is a member of the MAX 7000A family of high-performance, 3.3-V EEPROM-based programmable logic devices (PLDs). Built on a second-generation Multiple Array MatriX (MAX) architecture, these devices provide densities ranging from 600 to 10,000 usable gates.
Key electrical features include a fast 4.5-ns pin-to-pin logic delay, enabling counter frequencies up to 227.3 MHz. The device operates with a 3.3-V core voltage and supports a MultiVoltTM I/O interface, making its I/O pins compatible with 5.0-V, 3.3-V, and 2.5-V logic levels. In-system programmability (ISP) is supported via an IEEE Std. 1149.1 (JTAG) interface.
This PLD is available in a 144-TQFP package, suitable for surface mount applications. It also features programmable interconnect array (PIA) for predictable performance and offers programmable slew-rate control for bus-friendly operation. Additional features include programmable power-saving modes and a programmable security bit for design protection.
| Qty | Low | High |
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| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The maximum logic delay is 4.5 nanoseconds.
It supports counter frequencies up to 227.3 MHz.
It is compatible with 5.0 V, 3.3 V, and 2.5 V logic levels.
Yes, it supports IEEE Std. 1149.1 (JTAG) in-system programmability.
It comes in a 144-TQFP surface-mount package.
