| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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37,020 pcs
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37020 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Nexperia PUMH18,115 is a dual NPN transistor with built-in bias resistors, also known as a Resistor-Equipped Transistor (RET). This configuration simplifies circuit design and reduces component count.
Key electrical specifications include a collector-emitter voltage (VCEO) of 50V and a maximum output current (IO) of 100mA per transistor. The device features integrated bias resistors with a typical R1 value of 4.7 kΩ and a typical R2/R1 ratio of 2.1. The saturation voltage (Vce(sat)) is a maximum of 100mV at 500µA collector current and 10mA base current.
This component is supplied in a compact 6-TSSOP, SC-88, or SOT-363 surface-mount package, making it suitable for applications where space is limited. The integrated resistors reduce pick-and-place costs and simplify board layout.
Applications for this transistor array include low current peripheral drivers and control of IC inputs, replacing general-purpose transistors in digital applications.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.99 | $0.99 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The collector-emitter voltage (VCEO) for the PUMH18,115 is 50V.
The maximum output current (IO) for the PUMH18,115 is 100mA.
The PUMH18,115 has an integrated bias resistor R1 with a typical value of 4.7 kΩ and a typical R2/R1 ratio of 2.1.
The PUMH18,115 is supplied in a 6-TSSOP, SC-88, or SOT-363 package.