| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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235 pcs
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235 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Nexperia PUMD9,115 is a dual NPN/PNP resistor-equipped transistor (RET) designed for surface-mount applications. This component integrates two transistors with built-in bias resistors, simplifying circuit design and reducing component count.
Key electrical specifications include a collector-emitter voltage (VCEO) of 50V and a maximum output current of 100mA per transistor. The integrated bias resistors have a typical value of 10 kΩ for R1 and a typical ratio of 4.7 for R2/R1, with specific values of R2 being 47 kΩ. The Vce saturation voltage is 100mV at 250µA collector current and 5mA base current, and the DC current gain (hFE) is a minimum of 100 at 5mA collector current and 5V Vce.
This device is housed in a compact 6-TSSOP, SC-88, or SOT-363 package, making it suitable for space-constrained designs. The surface-mount configuration facilitates automated assembly processes. The power dissipation is rated at 300mW.
The PUMD9,115 operates within a temperature range of -65°C to 150°C. Its design with integrated resistors makes it ideal for applications such as low current peripheral drivers and controlling IC inputs, replacing general-purpose transistors in digital applications.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.99 | $0.99 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The collector-emitter voltage (VCEO) for the PUMD9,115 is 50V.
The PUMD9,115 has a maximum output current capability of 100mA.
The PUMD9,115 has a typical input resistor (R1) of 10 kΩ and a typical resistor ratio (R2/R1) of 4.7, corresponding to R2 being 47 kΩ.
The PUMD9,115 is available in a 6-TSSOP, SC-88, or SOT-363 package.
The operating temperature range for the PUMD9,115 is from -65°C to 150°C.