| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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2,991 pcs
|
2991 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Nexperia PUMD3,115 is a surface-mount resistor-equipped transistor (RET) featuring both NPN and PNP configurations within a single package. This component is designed for applications requiring simplified circuit design and reduced component count, such as low current peripheral drivers and control of IC inputs.
Key electrical characteristics include a collector-emitter voltage (VCEO) of 50V and a maximum output current (IO) of 100mA. It incorporates built-in bias resistors with a typical value of 10kΩ for the input (R1) and a typical bias resistor ratio (R2/R1) of 1. The transistor type is 1 NPN, 1 PNP - Pre-Biased (Dual), with a typical DC current gain (hFE) of 30 at 5mA and 5V. The saturation voltage (Vce Sat) is a maximum of 150mV at 500µA and 10mA.
This device is housed in a compact 6-TSSOP, SC-88, or SOT-363 package, suitable for surface mounting. The PUMD3,115 is designed to replace general-purpose transistors in digital applications, reducing pick and place costs and simplifying overall circuit construction. It is AEC-Q101 qualified, indicating its suitability for demanding automotive and industrial environments.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.99 | $0.99 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The collector-emitter voltage (VCEO) for the PUMD3,115 is 50V.
The PUMD3,115 has a maximum output current (IO) of 100mA.
The typical value for the R1 bias resistor in the PUMD3,115 is 10kΩ.
The PUMD3,115 is supplied in a 6-TSSOP, SC-88, or SOT-363 package.
The RoHS status is RoHS3 Compliant.
The Moisture Sensitivity Level (MSL) is 1 Unlimited.