| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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103,020 pcs
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103020 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Nexperia PUMD15,115 is a dual NPN/PNP resistor-equipped transistor (RET) in a surface-mountable package. This component integrates bias resistors, simplifying circuit design and reducing component count.
Key electrical specifications include a 50V collector-emitter voltage (open base) and a maximum output current of 100mA per transistor. The integrated bias resistors have a typical value of 4.7 kΩ for R1. The transistor array is rated for a maximum power dissipation of 300mW.
Designed for applications such as low current peripheral drivers and control of IC inputs, the PUMD15,115 simplifies digital circuit designs. Its pre-biased nature and integrated resistors reduce pick and place costs and streamline assembly processes.
The component is housed in a 6-TSSOP, SC-88, or SOT-363 package, suitable for surface mounting. This configuration is ideal for space-constrained applications.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.99 | $0.99 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The collector-emitter voltage (open base) for the PUMD15,115 is 50V.
The typical bias resistor R1 value is 4.7 kΩ.
The maximum output current is 100mA.
The PUMD15,115 is available in a 6-TSSOP, SC-88, or SOT-363 package.
The PUMD15,115 is a surface mount device.