PTN3460IBS/F1MP
NXP Semiconductors
The NXP Semiconductors PTN3460IBS/F1MP is a DisplayPort to LVDS bridge IC. It enables connectivity between eDP sources and LVDS display panels.
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2,797 pcs
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2797 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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1,173 pcs
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1173 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The PTN3460IBS/F2MP from NXP Semiconductors is an embedded DisplayPort to LVDS bridge device. It facilitates connectivity between an (embedded) DisplayPort (eDP) source and an LVDS display panel by processing the incoming DP stream and converting it to LVDS format.
This IC supports DP v1.2a and v1.1a, and eDP v1.2 and v1.1, with Main Link operation at 1.62 Gbit/s or 2.7 Gbit/s over one or two lanes. It handles single or dual bus LVDS signaling with color depths of 18 or 24 bits per pixel, and a pixel clock frequency up to 112 MHz. LVDS data packing can be configured for VESA or JEIDA formats. The device also supports EDID ROM emulation, simplifying integration with panels that lack EDID ROM.
Designed for industrial applications, the PTN3460IBS/F2MP operates within a wide temperature range of -40 °C to +85 °C. It offers flexibility through multiple configuration options, including multi-level configuration pins, DP AUX interface, and I2C-bus interface. The device can be powered by a 3.3 V supply or dual supplies (3.3 V/1.8 V) and is housed in a 56-HVQFN 7 mm x 7 mm package with 0.4 mm pitch.
Key features include an embedded microcontroller and on-chip NVM for firmware updates, LVDS panel power-up/down sequencing control, and no requirement for an external timing reference. The PTN3460IBS/F2MP is suitable for various embedded systems requiring DisplayPort to LVDS conversion.
| Qty | Low | High |
|---|---|---|
| 1+ | $6.39 | $6.39 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The operating temperature range is -40 °C to +85 °C.
It is available in a 56-HVQFN (7x7) package.
It can be powered by either a 3.3 V supply only or dual supplies (3.3 V/1.8 V).
It is compliant to DP v1.2a and v1.1a, and eDP v1.2 and v1.1.
The maximum pixel clock frequency is 112 MHz.
Yes, it can emulate EDID ROM behavior to support panels without EDID ROM.