PIMH9,115

The Nexperia PIMH9,115 is a dual NPN Resistor-Equipped Transistor (RET) in a compact surface-mount package. This component integrates two NPN transistors with built-in bias resistors, simplifying circuit design and reducing component count.

Key electrical specifications include a 50V collector-emitter voltage (VCEO) and a 100mA maximum output current (IO). The integrated bias resistors consist of R1 at 10 kΩ and R2 at 47 kΩ, facilitating direct connection to logic-level inputs. The transistor exhibits a typical saturation voltage of 100mV at 250µA base and 5mA collector current, with a minimum DC current gain (hFE) of 100 at 5mA collector current and 5V collector-emitter voltage.

Packaged in a 6-TSOP (SC-74, SOT-457) format, the PIMH9,115 is suitable for applications requiring reduced component count and simplified board layout. Its features make it ideal for low-current peripheral driving and control of IC inputs in digital applications. The device has a maximum power dissipation of 600mW and is supplied on tape and reel.

This RET simplifies circuit design by providing built-in bias resistors, reducing the need for external components. Its small package size and integrated functionality contribute to reduced pick-and-place costs and a smaller overall footprint in electronic designs.