| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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73,020 pcs
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73020 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Nexperia PDTC114TU,115 is an NPN Resistor-Equipped Transistor (RET) designed for digital applications. This pre-biased transistor simplifies circuit design by incorporating built-in bias resistors, reducing component count and pick-and-place costs.
Key electrical specifications include a collector-emitter voltage (VCEO) of 50V and an output current (IO) capability of 100mA. It features an input bias resistor (R1) of 10 kΩ, with a typical DC current gain (hFE) of 200 at 1mA and 5V. The saturation voltage (Vce(sat)) is a maximum of 150mV at 500µA and 10mA. The device has a power dissipation rating of 200 mW.
This transistor is housed in a compact SOT-323 surface-mount package, also referred to as SC-70. Its design makes it a cost-saving alternative for BC847 series transistors in digital applications, suitable for controlling IC inputs and switching loads.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.17 | $1.17 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The collector-emitter voltage (VCEO) for the PDTC114TU,115 is 50V.
The PDTC114TU,115 transistor has an output current (IO) capability of 100mA.
The integrated bias resistor R1 in the PDTC114TU,115 is 10 kΩ.
The PDTC114TU,115 transistor is supplied in a SOT-323 package, also known as SC-70.
The DC Current Gain (hFE) of the PDTC114TU,115 is a minimum of 200 at 1mA and 5V.