| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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4 pcs
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4 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Manufacturer Name | |
| Inputs | |
| Propagation Delay | |
| Storage Temperature | |
| Tape & Reel |
The PALCE22V10-25JC from CYP is an advanced PAL device built with zero-power, high-speed, electrically erasable CMOS technology. It provides user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count.
This device features a fast propagation delay of 5 ns and a maximum external frequency (fMAX) of 142.8 MHz. It includes 12 inputs and 10 I/O macrocells, each programmable as registered or combinatorial, and active-high or active-low to match application needs. The PALCE22V10Z variant offers zero standby power with a maximum standby current of 30 µA, enabling extended battery-powered operation.
The PALCE22V10 architecture implements the sum of products logic function, with a programmable AND array driving a fixed OR array. Product terms are distributed with varied counts from 8 to 16 across the outputs. Complex interconnections are placed on silicon for easy modification during prototyping or production.
Available in 24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC packages, the PALCE22V10-25JC is suitable for designs requiring flexible logic implementation and reduced board space.
| Qty | Low | High |
|---|---|---|
| 1+ | $2.23 | $2.23 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The propagation delay is 5 ns.
The maximum external frequency is 142.8 MHz.
The device has 10 I/O macrocells.
It is available in 24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC packages.
The PALCE22V10Z has a maximum standby current of 30 µA.