| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
3 pcs
|
3 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Inputs | |
| Propagation Delay | |
| Storage Temperature | |
| Tape & Reel |
The CYP PALCE22V10-10DMB is a programmable logic device (PLD) from the PALCE22V10 family, built using electrically erasable CMOS technology. It is designed to replace conventional SSI/MSI gates and flip-flops, reducing chip count and board space.
This device offers a fast propagation delay of 5 ns and an external fMAX of 142.8 MHz, making it suitable for high-speed applications. It features 12 inputs and 10 I/O macrocells, each programmable as registered or combinatorial, and active-high or active-low outputs. The architecture supports a sum-of-products implementation with a varied product term distribution, allowing up to 16 product terms per output for complex logic functions.
The PALCE22V10-10DMB is available in multiple package options, including 24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC. Its user-programmable nature allows for easy modification during prototyping and production, simplifying design implementation.
For the zero-power version, the PALCE22V10Z offers significantly reduced standby current (30 µA maximum), enabling extended battery-powered operation. This version also includes an unused product term disable feature.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The maximum propagation delay is 5 nanoseconds.
The maximum external frequency is 142.8 MHz.
It has 12 inputs.
It is available in 24-Pin Skinny DIP, 24-Pin SOIC, and 28-Pin PLCC packages.
Yes, it is RoHS3 compliant.