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13 pcs
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13 pcs | On Request | 1 | On Request | On Request | 1103 | On Request | On Request |
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The Lattice LFE2M20E-5FN256C is a Field Programmable Gate Array (FPGA) belonging to the LatticeECP2/M family. This device offers a logic density of 19000 LUTs and supports 140 I/O pins, making it suitable for system integration tasks.
Key features include embedded SERDES capabilities with data rates up to 3.125 Gbps and up to 16 channels, along with sysDSP blocks for high-performance multiply and accumulate operations. The FPGA provides flexible memory resources with embedded block RAM (EBR) and distributed RAM, as well as sysCLOCK Analog PLLs and DLLs for clock management.
Designed for high performance and cost-effectiveness, the LFE2M20E-5FN256C utilizes 90nm technology. It supports a wide range of interfaces through its programmable sysIO buffer, including LVTTL, LVCMOS, SSTL, HSTL, and differential standards. The device is configured using a 256-pin FBGA package, suitable for surface mounting.
This FPGA is designed for applications requiring advanced features like high-speed serial communication and digital signal processing. Its robust feature set and flexible I/O options make it a versatile component for various embedded systems.
The LFE2M20E-5FN256C FPGA has 19000 logic elements and 2375 LABs.
The LFE2M20E-5FN256C FPGA provides 140 I/O pins.
The LFE2M20E-5FN256C FPGA operates at 1.2V.
The LFE2M20E-5FN256C FPGA is supplied in a 256-FBGA package.
The LatticeECP2/M family features embedded SERDES with data rates from 250 Mbps to 3.125 Gbps, supporting up to 16 channels per device.
The LatticeECP2/M family offers flexible memory resources including 55Kbits to 5308Kbits of sysMEM Embedded Block RAM (EBR) and 12K to 202Kbits of distributed RAM.