| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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150 pcs
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150 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Lattice LFE2-20E-6FN672C is a Field Programmable Gate Array (FPGA) from the LatticeECP2/M family. It offers a logic density of 21,000 LUTs and provides 402 I/O pins for system integration.
This FPGA features flexible memory resources with 282,624 total RAM bits and 2,625 LABs. It supports embedded SERDES with data rates from 250 Mbps to 3.125 Gbps across up to 16 channels. The device includes sysDSP blocks for high-performance multiply and accumulate operations and sysCLOCK Analog PLLs and DLLs for clock management.
Designed for system integration, the LFE2-20E-6FN672C supports a wide range of interfaces through its programmable sysI/O buffer, including LVTTL, LVCMOS, SSTL, HSTL, and differential standards like LVDS and LVPECL. It also supports DDR and DDR2 memory.
The device is configured for surface mounting and comes in a 672-FPBGA package. It operates within a temperature range of 0°C to 85°C (TJ) and requires a voltage supply between 1.14V and 1.26V.
The LFE2-20E-6FN672C FPGA has 21,000 logic elements.
The LFE2-20E-6FN672C has 402 I/O pins.
The operating voltage range for the LFE2-20E-6FN672C is 1.14V to 1.26V.
The LFE2-20E-6FN672C is supplied in a 672-FPBGA (27x27) package.
The operating temperature range for this FPGA is 0°C to 85°C (TJ).
The LatticeECP2/M family supports embedded SERDES data rates from 250 Mbps to 3.125 Gbps.
The LatticeECP2/M family offers sysMEM Embedded Block RAM (EBR) and distributed RAM.