| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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28 pcs
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28 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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4 pcs
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4 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Lattice Semiconductor LFE2-12E-6FN484C is a Field Programmable Gate Array (FPGA) from the LatticeECP2/M family. It offers a logic density of 12,000 LUTs and provides 297 I/O pins for system integration. The device includes 226,304 total RAM bits, distributed across flexible memory resources.
This FPGA operates within a voltage range of 1.14V to 1.26V and has an operating temperature range of 0°C to 85°C (TJ). It is housed in a 484-FPBGA (23x23) package and is designed for surface mounting.
The LatticeECP2/M family supports embedded SERDES with data rates from 250 Mbps to 3.125 Gbps, sysDSP blocks for high-performance multiply and accumulate operations, and sysCLOCK Analog PLLs and DLLs for clock management. The programmable sysI/O buffer supports a wide range of interfaces, including LVTTL, LVCMOS, SSTL, HSTL, and differential standards like LVDS and LVPECL.
The LFE2-12E-6FN484C FPGA has 12000 logic elements.
The LFE2-12E-6FN484C offers 297 I/O pins.
The operating voltage range for the LFE2-12E-6FN484C is 1.14V to 1.26V.
The LFE2-12E-6FN484C is supplied in a 484-FPBGA (23x23) package.
The operating temperature range for this FPGA is 0°C to 85°C (TJ).
The embedded SERDES in the LatticeECP2/M family supports data rates up to 3.125 Gbps.
The LatticeECP2/M family offers between 55 Kbits and 5308 Kbits of Embedded Block RAM (EBR).