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1,000 pcs
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1000 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Lattice Semiconductor LFE2-12E-5TN144C is a Field Programmable Gate Array (FPGA) from the LatticeECP2/M family. It offers a logic density of 12,000 LUTs and supports 93 I/O pins. The device is equipped with 226,304 total RAM bits and 1,500 LABs.
This FPGA operates within a voltage range of 1.14V to 1.26V and has an operating temperature range of 0°C to 85°C (TJ). It supports various I/O standards including LVTTL, LVCMOS, SSTL, and HSTL. The device is configured in a 144-TQFP package with surface mount mounting type.
Key features include embedded SERDES capabilities with data rates from 250 Mbps to 3.125 Gbps, sysDSP blocks for high-performance multiply and accumulate operations, and flexible memory resources with embedded block RAM and distributed RAM. The device also incorporates sysCLOCK Analog PLLs and DLLs for clock management and programmable sysI/O buffers.
The LatticeECP2/M family data sheet highlights features such as high logic density for system integration, embedded SERDES, sysDSP blocks, flexible memory resources, sysCLOCK Analog PLLs and DLLs, pre-engineered source synchronous I/O, and programmable sysI/O buffers. Device configuration options include 1149.1 Boundary Scan compliance and an SPI boot flash interface.
The LFE2-12E-5TN144C FPGA has 12,000 logic elements.
The LFE2-12E-5TN144C FPGA has 93 I/O pins.
The LFE2-12E-5TN144C FPGA has a total of 226,304 RAM bits.
The LFE2-12E-5TN144C FPGA operates within a voltage range of 1.14V to 1.26V.
The LFE2-12E-5TN144C FPGA operates between 0°C and 85°C (TJ).
The LFE2-12E-5TN144C FPGA is supplied in a 144-TQFP package.
The LatticeECP2/M family supports embedded SERDES data rates from 250 Mbps to 3.125 Gbps.