| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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2,010 pcs
|
2010 pcs | On Request | 1 | On Request | On Request | 24+ | On Request | On Request | |
|
531 pcs
|
531 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Delay Time tpd(1) Max | |
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| Number of I | |
| Number of I/O | |
| Number of Logic Elements | |
| Number of Macrocells | |
| Operating Temperature | |
| Programmable Type | |
| Supplier Device Package | |
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| Voltage Supply |
The Lattice Semiconductor LC4256V-75TN100I is a high-performance, In-System Programmable CPLD from the ispMACH 4000V/B/C family. This device offers 256 macrocells and 64 I/O pins, with a maximum operating frequency of 400MHz and a propagation delay of 7.5ns.
Designed for ease of integration, it operates with supply voltages between 3V and 3.6V and supports 5V tolerant I/O. The CPLD features enhanced macrocells with individual control signals and wide input gating for complex logic functions.
This component is supplied in a 100-TQFP (14x14) package, suitable for surface mounting. It operates within a junction temperature range of -40°C to 105°C. The device is also IEEE 1149.1 boundary scan testable and uses an IEEE 1532 compliant interface for in-system programming.
The maximum operating frequency is 400 MHz.
The propagation delay is 7.5 ns.
The device operates with supply voltages from 3V to 3.6V.
The operating temperature range is -40°C to 105°C junction.
It is supplied in a 100-TQFP (14x14) surface mount package.
This CPLD has 256 macrocells.
There are 64 I/O pins available.