| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
1,622 pcs
|
1622 pcs | On Request | 1 | On Request | On Request | 1048+ | On Request | On Request | |
|
102 pcs
|
102 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Delay Time tpd(1) Max | |
| Mounting Type | |
| Number of Gates | |
| Number of I | |
| Number of Logic Elements | |
| Number of Macrocells | |
| Operating Temperature | |
| Programmable Type | |
| Propagation Delay | |
| Supplier Device Package | |
| Tape & Reel | |
| Voltage Supply |
The Lattice Semiconductor ISPLSI 2064A-80LT100 is a high-density, in-system programmable Complex Programmable Logic Device (CPLD). It offers 2000 PLD gates and 64 macrocells, providing ample logic capacity for various applications.
This CPLD operates within a supply voltage range of 4.75V to 5.25V and features a maximum propagation delay of 15 ns, with a maximum operating frequency of 125 MHz. It is designed for TTL compatible inputs and outputs and is electrically erasable and reprogrammable.
The device is housed in a 100-TQFP (14x14) package and supports surface mount installation. It operates within a temperature range of 0°C to 70°C (TA). The ispLSI 2064A series is built on a 0.35 micron E2CMOS technology and offers lead-free package options.
Key features include 64 I/O pins, four dedicated inputs, and three dedicated clock input pins. The device also includes a Global Routing Pool (GRP) for complete interconnectivity. It is fully form and function compatible with the ispLSI 2064, with identical timing specifications and packaging.
The maximum operating frequency is 125 MHz.
The propagation delay is 7.5 ns according to the datasheet, and 15 ns according to the product data.
The operating voltage is between 4.75V and 5.25V.
The operating temperature range is 0°C to 70°C (TA).
It is supplied in a 100-TQFP (14x14) package, also referred to as 100-LQFP.
The device has 64 macrocells.
The device contains 2000 PLD gates.