| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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5 pcs
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5 pcs | On Request | 1 | On Request | On Request | 9925 | On Request | On Request |
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The Altera EPM5032DI25 is an Erasable Programmable Logic Device (EPLD) from the MAX 5000 family, designed as a high-speed, high-density replacement for SSI and MSI TTL/CMOS packages.
This CPLD features a 15ns combinatorial delay, a counter frequency of up to 100 MHz, and a pipelined data rate of 100 MHz. It supports high-complexity designs with system clock rates up to 66 MHz. The device is housed in a DIP-28 package.
These EPLDs combine an innovative architecture with advanced processes to deliver optimum performance, logic density, and flexibility. They are suitable for design tasks ranging from fast address decoders to custom peripheral integration, saving board area and reducing power consumption.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The combinatorial delay is 15 ns.
The maximum counter frequency is 100 MHz.
The pipelined data rate is 100 MHz.
The system clock rate for high-complexity designs is up to 66 MHz.
The EPM5032DI25 is available in a DIP-28 package.
The EPM5032DI25 is RoHS3 Compliant.
The Moisture Sensitivity Level (MSL) is 1 Unlimited.
