| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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19,320 pcs
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19320 pcs | On Request | 1 | On Request | On Request | 18+ | On Request | 2026-06-03 12:15:10 | |
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12,053 pcs
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12053 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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5,400 pcs
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5400 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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94 pcs
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94 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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5 pcs
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5 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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1 pcs
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1 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EPM3128ATC100-10N is a member of the MAX 3000A family of programmable logic devices (PLDs). Built on a MAX architecture, these devices offer high performance and low cost, utilizing CMOS EEPROM technology. This specific model provides 128 macrocells and 2500 usable gates, with a pin-to-pin logic delay of 5.0 ns and a counter frequency of up to 192.3 MHz.
The device supports 3.3-V in-system programmability (ISP) via an IEEE Std. 1149.1 JTAG interface. It features a MultiVolt I/O interface, allowing the core to operate at 3.3 V while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels. The EPM3128ATC100-10N is available in a QFP package and is designed for industrial temperature ranges.
Additional features include built-in boundary-scan test (BST) circuitry, enhanced ISP capabilities for faster programming, and a programmable interconnect array (PIA) for predictable performance. The device also supports hot-socketing and has a bus-friendly architecture with programmable slew-rate control.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The device core operates at 3.3 V, with I/O pins compatible with 5.0-V, 3.3-V, and 2.5-V logic levels.
The EPM3128ATC100-10N is available in a QFP package.
The typical pin-to-pin logic delay is 5.0 ns.
The counter frequency is up to 192.3 MHz.
The device features 128 macrocells.
The Moisture Sensitivity Level (MSL) is 1 Unlimited.