| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
3 pcs
|
3 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Manufacturer Name | |
| Clock Rate | |
| Interface | |
| Mounting Type | |
| Non | |
| On | |
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| Voltage |
The ADSP-21065LKS-240 is a high-performance SHARC digital signal processor microcomputer from Analog Devices, designed for demanding applications in communications, audio, automotive, instrumentation, and industrial control. It is built on the Super Harvard Architecture (SHARC) with four independent buses enabling simultaneous data, instruction, and I/O fetch in a single cycle.
Key specifications include a 60 MHz clock rate delivering 66 MIPS, 198 MFLOPS peak, and 132 MFLOPS sustained floating-point performance. The device integrates 544 Kbits of on-chip SRAM (configurable as program or data memory) and supports an external address range of 64M words via an SDRAM controller. It includes a host interface, serial ports with I2S support, 12 programmable I/O pins, two timers, and DMA channels for both external port (2) and serial port (8).
The DSP operates at 3.3 V and is rated for 0°C to 85°C. It is supplied in a 208-lead surface mount MQFP package (28x28 mm). The ADSP-21065LKS-240 is code-compatible with the ADSP-2106x family, simplifying design migration.
The nominal supply voltage is 3.30 V.
The package is 208-BFQFP (MQFP) with supplier device package 208-MQFP (28x28).
The operating temperature range is 0°C to 85°C.
The RoHS status is listed as RoHS3 Compliant, but this is unverified and has low confidence.
The clock rate is 60 MHz.
The on-chip SRAM is 544 Kbits (68 kB), though the database lists 64 kB.
66 MIPS, 198 MFLOPS peak, 132 MFLOPS sustained.
