| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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2,006 pcs
|
2006 pcs | On Request | 1 | On Request | On Request | 24+ | On Request | On Request | |
|
4 pcs
|
4 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The ADN2812ACPZ is a clock and data recovery (CDR) IC with an integrated limiting amplifier, designed for high-speed serial data communication systems. It supports continuous data rates from 12.3 Mb/s to 2.7 Gb/s and automatically locks to all data rates without requiring an external reference clock or programming.
Key electrical specifications include a typical quantizer sensitivity of 6 mV, an adjustable slice level range of ±100 mV, and a loss of signal (LOS) detect range of 3 mV to 15 mV. The device operates from a single 3.3V supply with a typical power consumption of 750 mW. It features a 1:2 input-to-output ratio with differential CML input and output logic, and includes a PLL for clock recovery.
The ADN2812ACPZ is housed in a 32-lead LFCSP package with a 5 mm × 5 mm body size, suitable for surface mount assembly. It includes a loss of lock indicator and an I2C interface for accessing optional features. The device is designed for SONET/SDH applications and meets all SONET jitter requirements.
The operating temperature range is -40°C to 85°C.
It is available in a 32-lead LFCSP package with a 5 mm × 5 mm body size.
The supply voltage range is 3V to 3.6V, with a typical value of 3.3V.
The RoHS status is listed as RoHS3 Compliant, but this is unverified and should be treated as low confidence.
It supports continuous data rates from 12.3 Mb/s to 2.7 Gb/s.
The typical power consumption is 750 mW.
Yes, it includes an I2C interface for accessing optional features.