| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
7,020 pcs
|
7020 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Current | |
| Input Logic Level | |
| Latch-up Performance | |
| Logic Type | |
| Max Propagation Delay @ V, Max CL | |
| Mounting Type | |
| Number of Circuits | |
| Number of Inputs | |
| Operating Temperature | |
| SVHC Present | |
| Supplier Device Package | |
| Supplier Package | |
| Voltage |
The 74LVC2G32DP,125 from Nexperia is a dual 2-input OR gate integrated circuit designed for versatile applications. It features a wide supply voltage range from 1.65 V to 5.5 V, allowing it to function effectively in mixed 3.3 V and 5 V environments. The inputs are overvoltage tolerant up to 5.5 V, and Schmitt-trigger action provides tolerance for slower input rise and fall times, enhancing noise immunity.
This device offers a maximum propagation delay of 3.2 ns at 5V with a 50pF load capacitance. It supports input logic levels between 1.7V and 2V. The IC is specified for partial power-down applications using IOFF circuitry, which disables the output to prevent backflow current. The output drive capability is ±24 mA at VCC = 3.0 V, and latch-up performance exceeds 250 mA.
The 74LVC2G32DP,125 is available in an 8-TSSOP package, suitable for surface mounting. Its operating temperature range is -40°C to +125°C. The device complies with JEDEC standards JESD8-7, JESD8-5, JESD8C, and JESD36. ESD protection is provided, exceeding 2000 V for HBM (class 2) and 1000 V for CDM (class C3).
| Qty | Low | High |
|---|---|---|
| 1+ | $0.22 | $0.22 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
1.65V to 5.5V.
-40°C to +125°C.
8-TSSOP surface-mount package.
3.2 ns maximum at 5V and 50pF load.
±24 mA maximum at VCC = 3.0V.
Exceeds 2000V HBM and 1000V CDM.
OR Gate.