74AHC74PW,118

The Nexperia 74AHC74PW,118 is a high-speed Si-gate CMOS dual D-type flip-flop. It is pin compatible with Low-Power Schottky TTL (LSTTL) and specified in compliance with JEDEC standard No. 7-A.

This device features individual data inputs (D), clock inputs (CP), set inputs (SD), and reset inputs (RD), along with complementary outputs (Q and Q). The set and reset inputs are asynchronous active LOW and operate independently of the clock. Data is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The clock input includes Schmitt-trigger action, making the circuit tolerant to slower clock rise and fall times.

Key electrical specifications include an operating voltage range of 2V to 5.5V, a clock frequency of 115 MHz, and a maximum propagation delay of 9.3ns at 5V with a 50pF load. It draws a quiescent current of 2 µA and has an input capacitance of 3 pF. The operating temperature range is -40°C to +125°C (TA).

The 74AHC74PW,118 is supplied in a 14-TSSOP package with surface mount mounting type. The package dimensions are 0.173 inches (4.40mm) in width. It offers multiple package options and is specified for extended temperature ranges.