74AHC74D,118

The Nexperia 74AHC74D,118 is a high-speed Si-gate CMOS dual D-type flip-flop. It is pin compatible with Low-Power Schottky TTL (LSTTL) and specified in compliance with JEDEC standard No. 7-A.

This device features individual data inputs (D), clock inputs (CP), set inputs (SD), and reset inputs (RD). It also has complementary outputs (Q and Q). The set and reset inputs are asynchronous active LOW and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The clock input includes Schmitt-trigger action, making the circuit tolerant to slower clock rise and fall times.

Key electrical specifications include an operating voltage range of 2V to 5.5V, a clock frequency of 115 MHz, and a maximum propagation delay of 9.3ns at 5V and 50pF. The input current is a low 2 µA, and input capacitance is 3 pF. It operates across a wide temperature range of -40°C to +125°C.

The 74AHC74D,118 is available in a 14-SOIC surface mount package with a body width of 3.9 mm. It offers balanced propagation delays and accepts voltages higher than VCC. ESD protection is provided, with HBM exceeding 2000V (class 2) and CDM exceeding 1000V (class C3).