| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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83 pcs
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83 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| SVHC Present | |
| Tape & Reel |
The Renesas 5V991A-2JG is a high fanout, 3.3V PLL-based clock driver suitable for demanding computing and data-communication systems. A key feature is its programmable skew capability, allowing outputs to lead or lag the reference input signal.
This device provides eight programmable skew outputs organized in four banks of two. The skew is controlled via 3-level input signals that can be hard-wired. It operates with a core voltage of 3.3V and supports input frequencies from 3.75 to 85 MHz, with a corresponding output frequency range of 3.75 to 85 MHz.
The 5V991A-2JG features a maximum C-C jitter of 200 ps and a maximum output skew of 250 ps. It is housed in a 32-lead PLCC package with dimensions of 13.97 x 11.43 x 2.79 mm and a pitch of 1.27 mm. The operating temperature range is from 0°C to 70°C. The component is RoHS3 compliant and has a Moisture Sensitivity Level (MSL) of 1 Unlimited.
| Qty | Low | High |
|---|---|---|
| 1+ | $2.02 | $2.02 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The operating voltage is 3.3V.
The device is packaged in a 32-lead PLCC (Plastic Leaded Chip Carrier) with dimensions 13.97 x 11.43 x 2.79 mm and a 1.27 mm pitch.
The operating temperature range is 0°C to 70°C.
It provides 8 LVCMOS outputs arranged in 4 banks.
Yes, it includes a feedback input.
Both input and output are LVCMOS (Low-Voltage CMOS).
The maximum peak-to-peak cycle-to-cycle jitter is 200 picoseconds.