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XC2C256-6VQ100C The Xilinx XC2C256-6VQ100C is a CoolRunner-II family CPLD offering 256 macrocells and 6K gates. It operates at 1.8V and features a fast propagation delay.
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XC2C256-6VQ100C

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Mfr Name: Xilinx
Xilinx
The Xilinx XC2C256-6VQ100C is a CoolRunner-II family CPLD offering 256 macrocells and 6K gates. It operates at 1.8V and features a fast propagation delay.
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XC2C256-6VQ100C Available from 1 distributor

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XC2C256-6VQ100C Specifications Quick View

Most important parameters for selection – full specs in datasheet.
Category
Manufacturer Name
Frequency
Lead Spacing
Lead Style
Operating Voltage
Propagation Delay
Technology
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XC2C256-6VQ100C Description

Short technical summary and product information.

The XC2C256-6VQ100C is a Complex Programmable Logic Device (CPLD) from Xilinx's CoolRunner-II family. This CPLD is designed for digital logic implementation, state machine design, interface bridging, and system glue logic.

 

Key specifications include 256 macrocells, 6K gates, and a maximum operating frequency of 256MHz. It utilizes 0.18um CMOS technology and operates at a voltage of 1.8V. The device offers 256 product terms per macrocell and supports up to 82 user I/O pins, along with dedicated high-speed clock pins.

 

Packaged in a 100-pin VTQFP, the XC2C256-6VQ100C is suitable for various customization of digital circuits. Its architecture is built on the CoolRunner-II CPLD architecture, known for low power consumption and fast propagation delay.

 

This CPLD is an active lifecycle product. It is available in a VTQFP-100 package, designed for surface mounting.

XC2C256-6VQ100C Quick Information

Product Type: CPLD
Series: CoolRunner-II
Canonical Name: Xilinx XC2C256-6VQ100C CPLD
Subcategory: CPLD

XC2C256-6VQ100C Compliance

RoHS Status: RoHS Compliant
Moisture Sensitivity Level (MSL): 1 Unlimited
REACH Status: REACH Unaffected

XC2C256-6VQ100C Estimated Pricing

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1+ $0.50 $0.50

Estimated market price range - modelled values for guidance only, not live distributor offers.

XC2C256-6VQ100C Features

  • CoolRunner-II CPLD architecture.
  • 256 macrocells and 6K gates.
  • Operates at 1.8V supply voltage.
  • Features 256MHz maximum frequency.
  • Available in VTQFP-100 package.

XC2C256-6VQ100C Applications

  • Digital logic implementation.
  • State machine design.
  • Interface bridging.
  • System glue logic.
  • Customization of digital circuits.

XC2C256-6VQ100C FAQs

7 frequently asked questions generated from this part’s specifications.
How many macro cells does the XC2C256-6VQ100C have?

256 macro cells.

What is the gate count of the XC2C256-6VQ100C?

6K gates (6,000 usable gates).

What is the maximum operating frequency?

256MHz.

What is the operating voltage of the XC2C256-6VQ100C?

1.8V.

What package does the XC2C256-6VQ100C come in?

VTQFP-100 (100-pin Very Thin Quad Flat Pack).

How many user I/O pins are available?

Up to 82 user I/O pins.

What technology is used in the XC2C256-6VQ100C?

0.18um CMOS technology.

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