XC2C128-6CP132C

The Xilinx XC2C128-6CP132C is a high-performance, low-power Complex Programmable Logic Device (CPLD) from the CoolRunner-II family. This device is designed for applications requiring both speed and power efficiency, such as high-end communication equipment and battery-operated devices.

Key specifications include 128 macrocells and 3K gates, built on a 0.18um technology process. It operates at a maximum frequency of 244MHz and requires a supply voltage of 1.8V. The CPLD is housed in a 132-pin CSBGA package.

The CoolRunner-II architecture utilizes eight Function Blocks interconnected by an Advanced Interconnect Matrix (AIM). Each Function Block contains a 40x56 P-term PLA and 16 macrocells, offering flexibility for combinational or registered operation. Features like slew rate limiting, bus hold, pull-up, open drain, and programmable grounds are available on output pins. Schmitt-trigger inputs are also supported on a per-pin basis.

Additional features include global and local clocking options, global set/reset control, and per-macrocell product terms for advanced signal control. The DualEDGE flip-flop and CoolCLOCK features enable high-performance synchronous operation at lower clock frequencies, contributing to reduced power consumption. DataGATE functionality helps lower power by selectively disabling unused inputs.