| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
4 pcs
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4 pcs | On Request | 1 | On Request | On Request | 04+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Operating Voltage | |
| SVHC Present |
The Xilinx XC18V512SI is an in-system-programmable configuration PROM, part of a 3.3V family offering 512-kilobit to 4-megabit densities. It provides a cost-effective solution for storing and reprogramming Xilinx FPGA configuration bitstreams.
Key features include an endurance of 20,000 program/erase cycles over an industrial temperature range of -40°C to +85°C. The device supports dual configuration modes: serial slow/fast configuration up to 33 MHz and parallel configuration up to 264 Mb/s at 33 MHz. It also features 5V-tolerant I/O pins and 3.3V or 2.5V output capability.
Available in SO20L and other packages, the XC18V512SI is designed for simple interface to FPGAs and can be cascaded for storing longer or multiple bitstreams. It utilizes an advanced CMOS FLASH process for low power consumption.
This configuration PROM is suitable for applications requiring reliable and efficient FPGA bitstream storage and reprogramming, supporting JTAG command initiation of standard FPGA configuration.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.50 | $1.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The XC18V512SI operates at 3.3V.
The XC18V512SI is available in the SO20L package, among others like PC20, PC44, and VQ44.
The XC18V512SI supports serial slow/fast configuration up to 33 MHz and parallel configuration up to 264 Mb/s at 33 MHz.
The XC18V512SI has an endurance of 20,000 Program/Erase Cycles.
Yes, the XC18V512SI features 5V-tolerant I/O pins.
Yes, the XC18V512SI supports IEEE Std 1149.1 Boundary-Scan (JTAG).