| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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45 pcs
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45 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The X20C04JI-15 from Intersil is a Nonvolatile Static RAM designed for various electronic applications. This component offers specific electrical characteristics crucial for system design.
Key electrical specifications include a read cycle time that can range from a minimum of 150 ns to a maximum of 300 ns. The chip enable access time is also within this range, from 150 ns to 300 ns. Furthermore, the address access time is similarly specified between 150 ns and 300 ns. The output enable access time is faster, with a minimum of 50 ns and a maximum of 150 ns. The device also specifies output in a low Z state with minimal delay, and output in a high Z state with specific timing parameters.
Additional timing parameters such as chip enable to output in low Z, output enable to output in low Z, chip disable to output in high Z, and output disable to output in high Z are detailed. The output hold from address change is also specified. These precise timing characteristics are essential for integrating the X20C04JI-15 into complex digital systems where timing is critical.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.92 | $1.92 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The read cycle time for the X20C04JI-15 ranges from 150 ns to 300 ns.
The chip enable access time is between 150 ns and 300 ns.
The address access time is specified as 150 ns to 300 ns.
The output enable access time is 50 ns to 150 ns.
The chip disable to output in high Z is 80 ns to 100 ns, and the output disable to output in high Z is also 80 ns to 100 ns.