| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
436 pcs
|
436 pcs | On Request | 1 | On Request | On Request | 9044 | On Request | On Request | |
|
145 pcs
|
145 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Access Time | |
| Lead Spacing | |
| Memory Type | |
| Mounting Type | |
| Operating Mode |
This Toshiba TMM2018AP-35 is a 2K x 8 CACHE SRAM memory integrated circuit. It offers a maximum access time of 35 nanoseconds and operates asynchronously.
The device is organized as 2K words by 8 bits and has a memory density of 16384 degrees. It requires a supply voltage ranging from 4.5V to 5.5V, with a nominal voltage of 5V.
The TMM2018AP-35 comes in a 0.300-inch wide plastic DIP-24 package, suitable for through-hole mounting. The operating temperature range is from 0°C to 70°C. The terminals are tin-lead finished and have a pitch of 2.54 mm.
Key electrical characteristics include its parallel data interface and asynchronous operating mode. This component is designed for applications requiring fast cache memory access.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.92 | $1.92 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The maximum access time (tACC) for the TMM2018AP-35 is 35 ns.
The supply voltage for the TMM2018AP-35 ranges from 4.5V to 5.5V, with a nominal value of 5V.
The TMM2018AP-35 is supplied in a 0.300-inch wide plastic DIP-24 package.
The operating temperature range for the TMM2018AP-35 is from 0°C to 70°C.