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SN74LVC126APWR The Texas Instruments SN74LVC126APWR is a quadruple bus buffer gate with 3-state outputs. It operates from 1.65V to 3.6V and is available in a 14-TSSOP package.
Mfr Part #:

SN74LVC126APWR

Available from 9 distributors
Mfr Name: Texas Instruments
Texas Instruments
The Texas Instruments SN74LVC126APWR is a quadruple bus buffer gate with 3-state outputs. It operates from 1.65V to 3.6V and is available in a 14-TSSOP package.
✓ Total Stock: 308,465 pcs
$ Price Range: $0.13

SN74LVC126APWR Available from 9 distributors

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Romaks Technologies ✓
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301,000 pcs
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Components Technology Group, Inc. ✓
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3,000 pcs
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Chanetech ✓
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1,800 pcs
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Xingangxin ✓
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1,321 pcs
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Smaxon Electronics ✓
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524 pcs
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MW.FEP S.p.A. ✓
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389 pcs
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Braun Electronic Components ✓
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384 pcs
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Speed Components Ltd ✓
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46 pcs
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RAD ✓
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1 pcs
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1 pcs On Request 1 On Request On Request On Request On Request On Request
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SN74LVC126APWR Specifications Quick View

Most important parameters for selection – full specs in datasheet.
Category
Manufacturer Name
Current
Input Voltage
Latch-up Performance
Lead Spacing
Logic Type
Mounting Type
Number of Bits per Element
Number of Elements
Operating Temperature
Output Type
Supplier Device Package
Supplier Package
Voltage
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SN74LVC126APWR Description

Short technical summary and product information.

The SN74LVC126APWR from Texas Instruments is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. This device features independent line drivers with three-state outputs, where each output is disabled when the associated output-enable (OE) input is low.

 

Key electrical characteristics include a wide operating voltage range of 1.65V to 3.6V and input voltage tolerance up to 5.5V. The device offers a maximum propagation delay of 4.7ns at 3.3V and exhibits excellent latch-up performance exceeding 250mA per JESD 17.

 

Packaged in a 14-TSSOP, the SN74LVC126APWR is suitable for surface mount applications. Its operating temperature range is specified from -40°C to 125°C (TA), making it robust for various environmental conditions. This buffer gate is ideal for applications requiring signal buffering and level translation within the specified voltage parameters.

 

This component is part of the SN74LVC126A series, known for its low-voltage operation and high-speed performance. The three-state outputs provide flexibility in bus interfacing and system design.

SN74LVC126APWR Quick Information

Product Type: Buffer Gate
Series: SN74LVC126A
Canonical Name: Texas Instruments SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs
Subcategory: Non-Inverting Buffer

SN74LVC126APWR Compliance

RoHS Status: RoHS Compliant
Moisture Sensitivity Level (MSL): 1 Unlimited
REACH Status: REACH Unaffected

SN74LVC126APWR Estimated Pricing

Qty Low High
1+ $0.13 $0.13

Estimated market price range - modelled values for guidance only, not live distributor offers.

SN74LVC126APWR Features

  • Quadruple bus buffer gate with 3-state outputs.
  • Operates from 1.65V to 3.6V supply voltage.
  • Inputs accept voltages up to 5.5V.
  • 14-TSSOP surface mount package.
  • Wide operating temperature range of -40°C to 125°C.

SN74LVC126APWR Applications

  • Ideal for bus buffering applications.
  • Suitable for logic level translation.
  • Used in systems requiring signal isolation.
  • General purpose digital logic interfacing.

SN74LVC126APWR FAQs

6 frequently asked questions generated from this part’s specifications.
What is the operating voltage range for the SN74LVC126APWR?

The SN74LVC126APWR operates from 1.65V to 3.6V.

What type of package is the SN74LVC126APWR in?

The SN74LVC126APWR is supplied in a 14-TSSOP package.

What is the operating temperature range for this buffer gate?

The operating temperature range for the SN74LVC126APWR is -40°C to 125°C (TA).

Does the SN74LVC126APWR have 3-state outputs?

Yes, the SN74LVC126APWR features 3-state outputs.

What is the maximum propagation delay of the SN74LVC126APWR?

The maximum propagation delay is 4.7ns at 3.3V.

What is the latch-up performance of the SN74LVC126APWR?

Latch-up performance exceeds 250mA per JESD 17.

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