| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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200,000 pcs
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200000 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
|
3,210 pcs
|
3210 pcs | On Request | 1 | On Request | On Request | 00+ | On Request | On Request |
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The SN74LS109ADR from Texas Instruments is a dual J-K positive-edge-triggered flip-flop integrated circuit. This component features independent flip-flops with preset and clear functions, allowing for direct set or reset operations regardless of other inputs. When preset and clear are inactive, data at the J and K inputs are transferred to the outputs on the positive-going edge of the clock pulse.
Key electrical specifications include a maximum clock frequency of 30 MHz and a typical supply current of 15000 µA. The device operates within a voltage range of 4.75V to 5.25V and can source/sink up to 8 mA and -0.4 mA respectively. The maximum propagation delay is rated at 40ns at 5V with a 15pF load capacitance.
Designed for surface mounting, the SN74LS109ADR comes in a 16-SOIC package with dimensions of 0.154 inches (3.90mm width). The operating temperature range is from 0°C to 70°C (TA). This flip-flop can be configured as a toggle flip-flop by grounding the K input and tying the J input high, or as a D-type flip-flop if J and K are tied together, offering design flexibility.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.71 | $0.71 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The SN74LS109ADR operates within a voltage range of 4.75V to 5.25V.
The SN74LS109ADR is supplied in a 16-SOIC package.
The operating temperature range for the SN74LS109ADR is 0°C to 70°C (TA).
The SN74LS109ADR is RoHS3 Compliant.
The Moisture Sensitivity Level (MSL) for the SN74LS109ADR is 1 Unlimited.
The maximum clock frequency for the SN74LS109ADR is 30 MHz.
The maximum propagation delay is 40ns at 5V with a 15pF load capacitance.