| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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45,200 pcs
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45200 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The SN65LVDS104DR from Texas Instruments is an active 1:4 LVDS clock fan-out buffer. It is designed to meet or exceed the requirements of the ANSI EIA/TIA-644 standard for low-voltage differential signaling.
This buffer supports data signaling rates up to 400 Mbps and clock frequencies up to 400 MHz. It features a typical propagation delay of 3.1 ns and operates from a single 3.3V supply. The input accepts LVDS signals with a typical differential input level of ±100 mV, and the output provides LVDS signaling with a typical output voltage of 350 mV into a 100-Ω load.
The SN65LVDS104DR is suitable for applications requiring low-power, low-noise coupling, and high switching speeds. It is available in a 16-SOIC surface mount package. The operating temperature range is -40°C to 85°C.
LVTTL levels are 5-V tolerant, and the driver outputs are high-impedance when disabled or with VCC < 1.5V. Bus-pin ESD protection exceeds 16 kV.
| Qty | Low | High |
|---|---|---|
| 1+ | $2.67 | $2.67 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The SN65LVDS104DR supports data signaling rates up to 400 Mbps.
The typical propagation delay for the SN65LVDS104DR is 3.1 ns.
The SN65LVDS104DR operates from a voltage range of 3V to 3.6V.
The SN65LVDS104DR operates within a temperature range of -40°C to 85°C.
The SN65LVDS104DR is available in a 16-SOIC package.
Yes, the receiver and drivers meet or exceed the requirements of the ANSI EIA/TIA-644 Standard.
The SN65LVDS104DR accepts differential input levels, typically ±100 mV.