| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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1,012 pcs
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1012 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The SN65DSI86ZXHR from Texas Instruments is a specialized interface bridge designed to convert MIPI DSI signals to embedded DisplayPort (eDP) signals. This device supports eDP 1.4 compliance with lane configurations of 1, 2, or 4 lanes, operating at speeds ranging from 1.62 Gbps (RBR) up to 5.4 Gbps (HBR2). It implements a MIPI D-PHY version 1.1 physical layer front-end and a DSI version 1.02.00 interface.
The bridge features a dual-channel DSI receiver configurable for one to four D-PHY data lanes per channel, each operating up to 1.5 Gbps. It supports DSI video packets in 18 bpp (RGB666) and 24 bpp (RGB888) formats. The SN65DSI86ZXHR is suitable for high-resolution applications, including 4K (4096 x 2304) at 60 fps with 18 bpp color, and WUXGA (1920 x 1200) with 3D graphics at 60 fps (120 fps equivalent).
Key electrical specifications include a 1.2-V main VCC supply and a 1.8-V supply for digital I/Os. Low-power features such as panel refresh and MIPI ultralow power state (ULPS) are supported. The device is configurable via I2C and supports external reference clock frequencies including 12 MHz, 19.2 MHz, 26 MHz, 27 MHz, and 38.4 MHz. The operating temperature range is -40°C to +85°C.
Packaged in a compact 64-ball 5x5 mm nFBGA (ZXH) with surface mount, the SN65DSI86ZXHR is designed for applications such as PC notebooks and tablets. It offers configurable DisplayPort lane polarity and assignment.
| Qty | Low | High |
|---|---|---|
| 1+ | $5.22 | $5.22 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
It supports Embedded DisplayPort 1.4 compliance.
It supports up to 4096 x 2304 resolution at 60 fps with 18 bpp color.
Lane speeds up to 5.4 Gbps (HBR2).
Available in 64-NFBGA (5x5) and 64-VFBGA packages.
The main VCC supply voltage is 1.2 V.
Yes, it supports panel refresh and MIPI ULPS.