PX1011BI-EL1/G,551

The PX1011BI-EL1/G,551 from NXP Semiconductors is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY). It is compliant with the PCI Express Base Specification, Rev. 1.1, and handles the low-level PCI Express protocol and signaling.

This PHY operates at 2.5 Gbit/s and features an 8-bit PXPIPE interface, which is an enhancement of the PHY Interface for the PCI Express (PIPE) specification. The 8-bit data interface operates at 250 MHz with SSTL_2 signaling, compatible with FPGA I/O interfaces. Key features include Clock and Data Recovery (CDR), data serialization and de-serialization (SerDes), 8b/10b encoding, elastic buffer, and receiver detection.

Designed for advanced power management, the PX1011BI-EL1/G,551 dissipates less than 300 mW in L0 normal mode and supports power management states L0, L0s, and L1. It requires a 100 MHz external reference clock with a tolerance of ±300 ppm and includes on-chip reference clock termination. The device also features a JTAG (IEEE 1149.1) boundary scan interface and a Built-In Self Test (BIST) controller.

The PX1011BI-EL1/G,551 is supplied in an 81-LFBGA (9x9) package and is designed for surface mounting. It operates at 1.2V and has an industrial operating temperature range of -40°C to +85°C. ESD protection is rated at 2000 V for the Human Body Model.