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2,500 pcs
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2500 pcs | On Request | 1 | On Request | On Request | 04+ | On Request | On Request |
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The PCK2509SLDH from NXP Semiconductors is a PLL-based clock driver, part of the PCK25 Series. It is engineered for PC100 and PC133 SDRAM applications, providing clock distribution with a frequency range of 50-150 MHz. This device offers a 1:9 clock driver configuration, with 9 true outputs and 0 inverted outputs.
The integrated Phase-Locked Loop (PLL) ensures stable clock generation. When outputs are disabled, the PLL and feedback output adjust to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be controlled individually. The component is housed in a PDSO24 package, suitable for surface mounting.
This clock driver is designed to facilitate efficient clock distribution in memory systems, contributing to the overall performance and stability of motherboards and other computing platforms.
The PCK2509SLDH operates within a frequency range of 50 to 150 MHz.
The PCK2509SLDH has 9 true outputs.
The PCK2509SLDH is supplied in a PDSO24 package.
The PCK2509SLDH provides a 1:9 clock driver ratio.