PALCE610H25JC

The Lattice Semiconductor PALCE610H25JC is a general-purpose Programmable Array Logic (PAL) device, functionally equivalent to the EP610. It is manufactured using advanced CMOS EE technology, providing low power consumption and high speed with a worst-case propagation delay (tPD) of 15 ns. This device can accommodate logic functions with up to 20 inputs and 16 outputs, utilizing 16 independently configurable I/O macrocells. Each macrocell can be configured as either registered or combinatorial, with registers programmable as D, T, J-K, or S-R flip-flops.

The PALCE610 architecture uses a sum-of-products logic with a programmable-AND and fixed-OR structure. Eight product terms are available to each macrocell for logic implementations. The device supports asynchronous clocking and features register preload for testability and power-up reset for initialization. It is offered in space-saving 24-pin SKINNYDIP and 28-pin PLCC packages, suitable for easy prototyping due to its ability to be quickly erased and reprogrammed. A security bit is available to protect proprietary designs.

This PAL device is well-suited for various logic implementation tasks where flexibility and speed are required. Its electrically erasable CMOS technology ensures efficient power usage, with a typical supply current (ICC) of 90 mA at high speed.