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69 pcs
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69 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Lattice Semiconductor PALCE610H15JC is a general-purpose Programmable Array Logic (PAL) device from the PALCE610 family. It offers 600 gates and 16 macrocells that can be individually configured for registered or combinatorial operation. The device supports D, T, J-K, or S-R flip-flop configurations for its registers.
This SPLD utilizes advanced CMOS EE technology, providing low power consumption with a typical ICC of 90mA at high speed. It boasts a fast propagation delay of 15ns. The PALCE610H-15JC is available in a space-saving 28-pin PLCC package.
Designed for flexibility, the macrocells can accommodate logic combinations with up to 20 inputs and 16 outputs. The device includes features like power-up reset for initialization and register preload for testability. It is manufactured using advanced CMOS EE technology, ensuring high reliability and 100% programming yield.
This part is noted as obsolete, with stock resources listed as factory excess stock or from franchised distributors. It is suitable for applications requiring programmable logic solutions where its specific gate count and macrocell configuration meet design requirements.
The PALCE610H-15JC operates at a nominal voltage of 5V.
The PALCE610H-15JC is available in a 28-pin PLCC package.
The PALCE610H-15JC features 16 macrocells.
The typical current consumption (ICC) for the PALCE610H-15JC at high speed is 90mA.
The propagation delay for the PALCE610H-15JC is a maximum of 15ns.
The RoHS status for the PALCE610H-15JC is listed as RoHS3 Compliant.
The Moisture Sensitivity Level (MSL) for the PALCE610H-15JC is Level 1.