| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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500 pcs
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500 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The NB3V8312CFAG is an ultra-low jitter, low skew 1:12 LVCMOS fanout buffer from On Semiconductor. It is capable of distributing clock signals from an LVCMOS/LVTTL input up to 250 MHz.
This buffer features 12 LVCMOS outputs that can drive terminated transmission lines. The outputs can be tri-stated via the OE input. It also includes a synchronous clock enable (CLK_EN) input that prevents output glitches when enabling or disabling the clock outputs.
With separate VDD core and V DDO output supplies, the NB3V8312CFAG offers flexibility in voltage configuration, supporting VDD core voltages of 3.3 V, 2.5 V, or 1.8 V, and V DDO output voltages of 3.3 V, 2.5 V, or 1.8 V, with the constraint that VDD must be greater than or equal to V DDO. This dual supply operation enables lower power consumption and output-level compatibility.
The device is available in a 32-pin LQFP package and is suitable for applications in networking, telecom, server and storage area networking, RRU LO reference distribution, medical, and test equipment.
| Qty | Low | High |
|---|---|---|
| 1+ | $4.44 | $4.44 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The maximum clock frequency for the NB3V8312CFAG is 250 MHz.
The NB3V8312CFAG accepts LVCMOS and LVTTL clock inputs.
The NB3V8312CFAG provides 12 LVCMOS clock outputs.
The maximum skew between outputs for the NB3V8312CFAG is 150 ps.
The NB3V8312CFAG operates with a voltage range of 1.6V to 3.465V, supporting independent VDD core and V DDO supplies.
The NB3V8312CFAG operates within a temperature range of -40°C to 85°C.
The NB3V8312CFAG is available in a 32-pin LQFP package.