| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
7,147 pcs
|
7147 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Channel Type | |
| Channels per Circuit | |
| Data Rate | |
| Input Signal | |
| Mounting Type | |
| Number of Circuits | |
| Operating Temperature | |
| Output Signal | |
| Output Type | |
| Propagation Delay | |
| Supplier Device Package | |
| Supplier Package | |
| Translator Type |
The NB100LVEP91DWG is a triple, any-level positive input to LVNECL output translator from ON Semiconductor. It is capable of translating various input logic levels, including LVPECL, LVTTL, LVCMOS, HSTL, CML, and LVDS, to differential LVNECL output signals. This device features a maximum input clock frequency exceeding 2.0 GHz and a maximum input data rate over 2.0 Gb/s, with a typical propagation delay of 500 ps.
The operating voltage range for this translator is VCC from 2.375 V to 3.8 V and VEE from -2.375 V to -3.8 V. The operating temperature range is -40°C to 85°C. The NB100LVEP91DWG is supplied in a 20-SOIC package with surface mount mounting type.
Under open input conditions, the Q outputs default to a low state, ensuring stability. The device requires three power rails (VCC, VEE, and GND) for operation, with recommended bypassing capacitors. The VBB pin is an internally generated voltage supply that can be used as a switching reference for single-ended or AC-coupled inputs.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.12 | $0.12 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The operating supply voltage range is 2.375 V to 3.8 V for VCC and -2.375 V to -3.8 V for VEE.
The NB100LVEP91DWG is available in a 20-SOIC surface mount package with a width of 7.50 mm.
The operating temperature range is -40°C to 85°C.
The maximum data rate is greater than 2.0 Gbps.
The typical propagation delay is 500 ps.
It supports CML, HSTL, LVCMOS, LVDS, LVPECL, and LVTTL input signals.
The output is differential LVNECL.