| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
92 pcs
|
92 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Mounting Type | |
| Operating Temperature |
The Zarlink Semiconductor MT8941BP is a dual digital phase-locked loop (DPLL) designed for synchronization and timing control in T1 and CEPT digital trunk transmission links. It provides a T1 clock at 1.544 MHz and a CEPT clock at 2.048 MHz, both locked to an 8 kHz reference clock.
This device utilizes low-power CMOS technology and offers typical inherent output jitter of 0.07 UI peak-to-peak. It also features significant jitter attenuation at various frequencies, with a minimum of 64 dB for 5 to 40 kHz. A jitter-free "FREE-RUN" mode is also available.
The MT8941BP is suitable for applications requiring precise timing signals for ST-BUS clock and frame pulse generation. It is available in a 28-pin PLCC package and operates within a temperature range of -40°C to +85°C.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.67 | $1.67 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The MT8941BP provides a T1 clock at 1.544 MHz, locked to an 8 kHz reference clock.
The MT8941BP provides a CEPT clock at 2.048 MHz, locked to an internal or external 8 kHz reference clock.
The typical inherent output jitter (unfiltered) for the MT8941BP is 0.07 UI peak-to-peak.
The MT8941BP operates in a temperature range of -40°C to +85°C.
The MT8941BP is available in a 28-pin PLCC package.