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45,000 pcs
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45000 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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This integrated circuit is a dual JK flip-flop designed for high-performance applications. It features negative-edge clocked operation and includes active-low asynchronous Set and Reset inputs, allowing for immediate state changes independent of the clock.
The device operates over a wide voltage range of 2.0V to 6.0V and supports a clock frequency of up to 35 MHz. Its outputs are complementary, capable of driving 10 LSTTL loads and directly interfacing with CMOS, NMOS, and TTL logic families. The maximum propagation delay is 21ns at 6V with a 50pF load.
Packaged in a 16-SOIC surface-mount configuration, this flip-flop is suitable for various digital logic designs. It has an operating temperature range of -55°C to 125°C (TA). The component is Pb-Free and meets JEDEC Standard No. 7A requirements.
Key features include its dual flip-flop structure, each handling 1 bit, and its ability to function as a toggle, set, or reset based on input conditions. The low input current and high noise immunity are characteristic of its CMOS construction.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.86 | $0.86 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The MC74HC112ADR2G operates within a voltage range of 2.0V to 6.0V.
The MC74HC112ADR2G is supplied in a 16-SOIC package, specifically a 16-SOIC (0.154", 3.90mm Width).
The MC74HC112ADR2G has an operating temperature range of -55°C to 125°C (TA).
The maximum clock frequency for the MC74HC112ADR2G is 35 MHz.
The maximum propagation delay for the MC74HC112ADR2G is 21ns when tested at 6V with a 50pF load.
The input capacitance of the MC74HC112ADR2G is 10 pF.