| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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2,020 pcs
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2020 pcs | On Request | 1 | On Request | On Request | 24+ | On Request | On Request | |
|
9 pcs
|
9 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Halogen Free | |
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| Translator Type |
The MC100EP91DWG from ON Semiconductor is a versatile triple any-level translator. This device accepts various positive input logic levels, including LVPECL, LVTTL, LVCMOS, HSTL, CML, and LVDS, and translates them into differential NECL output signals. It is designed for high-speed applications, featuring a maximum input clock frequency greater than 2.0 GHz and a maximum input data rate exceeding 2.0 Gb/s.
The translator operates with a VCC range of 2.375 V to 3.8 V and a VEE range of -3.0 V to -5.5 V. It offers a typical propagation delay of 500 ps. The device is housed in a 20-SOIC package, suitable for surface mounting. Under open input conditions, the outputs default to a stable state, ensuring system reliability. The MC100EP91DWG is Pb-Free, Halogen Free, and RoHS Compliant.
This translator is ideal for applications requiring level shifting between different logic families, particularly when interfacing with NECL systems. Its ability to accept multiple input standards makes it a flexible solution for complex digital designs. The operating temperature range is -40°C to 85°C.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.12 | $0.12 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The maximum input data rate is greater than 2.0 Gb/s.
The typical propagation delay is 500 ps.
The operating voltage range for VCC is 2.375 V to 3.8 V, and for VEE is -3.0 V to -5.5 V.
The operating temperature range is -40°C to 85°C.
The MC100EP91DWG is available in a 20-SOIC package.
The MC100EP91DWG accepts LVPECL, LVTTL, LVCMOS, HSTL, CML, or LVDS signals.
The MC100EP91DWG translates input signals to differential NECL output signals.