| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
364 pcs
|
364 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| AEC Qualified | |
| Automotive Grade | |
| Available Total Delays | |
| Delay Time | |
| Delay to 1st Tap | |
| Function | |
| Industrial Grade | |
| Medical Grade | |
| Military Grade | |
| Mounting Type | |
| Number of Independent Delays | |
| Number of Taps | |
| Operating Temperature | |
| Supplier Device Package | |
| Tap Increment | |
| Tape & Reel | |
| Voltage |
The MC100EP195BMNG is a 3.3 V ECL Programmable Delay Chip (PDC) from On Semiconductor, primarily used for clock deskewing and timing adjustments. It provides a variable delay for differential NECL/PECL input transitions.
The delay section features a programmable matrix of gates and multiplexers, offering digitally selectable resolutions of approximately 10 ps. The chip has a net delay range of up to 10.2 ns, with a fixed minimum delay of 2.2 ns. The delay is selected via 10 data select inputs (D[9:0]) and controlled by the LEN pin. The IN/IN inputs can accept LVPECL or LVDS level signals.
This device operates within a PECL mode voltage range of 3.0 V to 3.6 V (with VEE = 0 V) and an NECL mode range of VCC = 0 V with VEE = -3.0 V to -3.6 V. It has a typical maximum input clock frequency exceeding 1.2 GHz.
The MC100EP195BMNG is available in a 32-VFQFN Exposed Pad package and is designed for surface mounting. The operating temperature is specified up to 85°C.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.20 | $0.20 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The programmable delay range is from 2.2 ns to 12.2 ns.
The delay increment is 10 ps.
The operating voltage range is 3.0 V to 3.6 V in PECL mode.
The MC100EP195BMNG is in a 32-VFQFN Exposed Pad package.
The operating temperature is up to 85°C.