| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
1,135 pcs
|
1135 pcs | On Request | 1 | On Request | On Request | 17+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Differential | |
| Divider | |
| Frequency | |
| Input | |
| Lead Spacing | |
| Mounting Type | |
| Number of Circuits | |
| Operating Temperature | |
| Output | |
| PLL | |
| Ratio | |
| Supplier Device Package | |
| Tape & Reel | |
| Type | |
| Voltage |
The ON Semiconductor MC100EL34DR2G is a low skew clock generation chip designed for applications requiring precise clock signal alignment. It features internal dividers that are synchronous, ensuring common output edges are precisely aligned. The device supports both PECL and NECL operating modes, with a PECL operating voltage range of 4.2V to 5.7V and NECL range of -4.2V to -5.7V.
Key electrical characteristics include a maximum frequency of 1.1 GHz and an output-to-output skew of only 50 ps. It includes features like synchronous enable/disable and a master reset for synchronization. The chip is housed in a 16-SOIC package and is suitable for surface mounting. Internal input pulldown resistors are present on CLK, EN, and MR pins.
This clock generator is designed for applications where minimal clock jitter and precise timing are critical. Its synchronous operation and master reset capability aid in system synchronization, making it suitable for complex digital systems. The 100 Series includes temperature compensation for stable operation across its specified temperature range.
| Qty | Low | High |
|---|---|---|
| 1+ | $7.01 | $7.01 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The PECL mode operating voltage range is 4.2V to 5.7V.
The maximum frequency is 1.1 GHz.
The output-to-output skew is 50 ps.
It is supplied in a 16-SOIC package.
The operating temperature range is -40°C to 85°C.
Yes, it features synchronous enable/disable and a master reset for synchronization.