ST16C554CQ64-F
Exar
The MaxLinear ST16C554CQ64-F is a Quad UART Interface IC featuring 16-byte FIFOs. It supports a data rate of 1.5 Mbps and operates within a supply voltage range of 2.97V to 5.5V.
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23 pcs
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23 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Automotive Grade | |
| Industrial Grade | |
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The Lattice Semiconductor M5-192/120-7YC-10YI is a Complex Programmable Logic Device (CPLD) belonging to the MACH 5 family. This fifth-generation MACH architecture provides fast speeds at high CPLD densities, low power consumption, and supports features like in-system programmability and Boundary Scan testability.
Key electrical specifications include a pin-to-pin delay as fast as 5.5 ns for commercial applications and 7.5 ns for industrial use. It features a counter frequency of 182 MHz and supports operating voltages of 3.3V and 5V. The device offers macrocell densities ranging from 128 to 512 and I/O counts from 68 to 256.
Designed for high-speed computing, low-power applications, communications, and embedded control, this CPLD is ideal for PAL block device integration. It is manufactured using E2CMOS process technologies and comes in a PQFP160 package.
Advanced power management options allow for incremental power reduction while maintaining performance. The device is in-system programmable through an IEEE 1149.1 Test Access Port (TAP) interface, facilitating easy system integration.
| Qty | Low | High |
|---|---|---|
| 1+ | $2.21 | $2.21 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The pin-to-pin delay is as fast as 5.5 ns for commercial applications and 7.5 ns for industrial applications.
This CPLD supports both 3.3V and 5V operations.
The macrocell density ranges from 128 to 512 macrocells.
The device offers an I/O count ranging from 68 to 256 I/Os.
The counter frequency is 182 MHz.
The M5-192/120-7YC-10YI is supplied in a PQFP160 package.