| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
2,900 pcs
|
2900 pcs | On Request | 1 | On Request | On Request | 09+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| AEC Qualified | |
| Automotive Grade | |
| Industrial Grade | |
| Lead Style | |
| Medical Grade | |
| Military Grade | |
| Package / Case | |
| Power Dissipation | |
| SVHC Present | |
| Storage Temperature | |
| Voltage |
The ESMT M12L64164A-5TIG is a Synchronous DRAM organized as 4 x 1,048,576 words by 16 bits. This component features a JEDEC standard 3.3V power supply and LVTTL compatibility. Its synchronous design allows for precise cycle controls with the system clock, enabling I/O transactions on every clock cycle.
Key specifications include programmable CAS Latency (2 & 3), Burst Length (1, 2, 4, 8 & full page), and Burst Type (Sequential & Interleave). It also supports auto and self-refresh with a 15.6μs refresh interval. All inputs are sampled at the positive going edge of the system clock, and DQM is available for masking.
Packaged in a TSOP, this DRAM is suitable for various high bandwidth, high performance memory system applications. The absolute maximum ratings include a voltage on any pin relative to VSS of -1.0 ~ 4.6V, and a storage temperature range of -55 ~ +150℃. Power dissipation is rated at 1W.
The operating voltage is 3.3V.
It is 64Mb organized as 1M words x 16 bits x 4 banks.
CAS latency of 2 and 3 are supported.
Burst lengths of 1, 2, 4, 8 and full page are supported.
The refresh interval is 15.6 µs.
The power dissipation is 1 W.
It is available in TSOP package.