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9 pcs
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9 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Lattice LFE2M35E-6FN484C-5I is a Field-Programmable Gate Array (FPGA) belonging to the LatticeECP2/M family. This device is optimized for high performance and cost-effectiveness, utilizing 90nm technology. It features a flexible fabric with LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), and Delay Locked Loops (DLLs).
Key electrical specifications include a logic density ranging from 6K to 95K LUTs and 90 to 583 I/Os. The LatticeECP2M family, which this part belongs to, offers embedded SERDES with data rates from 250 Mbps to 3.125 Gbps across up to 16 channels, supporting protocols like PCI Express and Ethernet. It also incorporates sysDSP blocks, with 3 to 42 blocks available for high-performance multiply and accumulate operations.
This FPGA is housed in a BGA484 package. The LatticeECP2/M family is designed for applications requiring advanced features like DSP blocks and high-speed interfaces within an economical FPGA fabric. The ispLEVER design tool suite from Lattice facilitates efficient design implementation for this family.
| Qty | Low | High |
|---|---|---|
| 1+ | $4.72 | $4.72 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The logic density ranges from 6K to 95K LUTs.
It supports 90 to 583 I/Os.
The embedded SERDES supports data rates from 250 Mbps to 3.125 Gbps.
Up to 16 channels per device are available.
The package type is BGA484.
The RoHS status is RoHS3 Compliant.
The MSL is 1 Unlimited.