| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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2 pcs
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2 pcs | On Request | 1 | On Request | On Request | 817 | On Request | On Request |
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The Lattice LFE2M35E-6FN484C is a Field Programmable Gate Array (FPGA) belonging to the LatticeECP2/M family. This device offers a logic density of 34,000 LUTs and supports 303 I/O pins, making it suitable for complex system integration.
Key features include embedded SERDES capabilities with data rates up to 3.125 Gbps and up to 16 channels, sysDSP blocks for high-performance multiply-accumulate operations, and flexible memory resources with 2.15 Mbit of embedded block RAM and distributed RAM. The device operates within a voltage range of 1.14V to 1.26V and has an operating temperature range of 0°C to 85°C (TJ).
Designed for high performance and cost-effectiveness, the LatticeECP2/M family utilizes advanced architecture and 90nm technology. The LFE2M35E-6FN484C is packaged in a 484-FPBGA (23x23 mm) and is designed for surface mounting.
This FPGA supports a wide range of interfaces through its programmable sysI/O buffers and includes features like PLLs and DLLs for clock management. Configuration options include 1149.1 Boundary Scan compliance and SPI boot flash interface.
The LFE2M35E-6FN484C FPGA has 34000 logic elements.
The LFE2M35E-6FN484C FPGA has 303 I/O pins.
The operating voltage range for the LFE2M35E-6FN484C FPGA is 1.14V to 1.26V.
The LFE2M35E-6FN484C FPGA is supplied in a 484-FPBGA (23x23) package.
The embedded SERDES in the LatticeECP2M family supports data rates from 250 Mbps to 3.125 Gbps.
LatticeECP2/M family devices offer 55Kbits to 5308Kbits of embedded block RAM.
